Datasheet

50.7.2 TC Channel Mode Register: Capture Mode
Name: TC_CMRx
Offset: 0x04 + x*0x40 [x=0..2]
Reset: 0x00000000
Property: Read/Write
This register can be written only if the WPEN bit is cleared in the TC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SBSMPLR[2:0] LDRB[1:0] LDRA[1:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WAVE CPCTRG ABETRG ETRGEDG[1:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST[1:0] CLKI TCCLKS[2:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 22:20 – SBSMPLR[2:0] Loading Edge Subsampling Ratio
Value Name Description
0
ONE Load a Capture register each selected edge.
1
HALF Load a Capture register every 2 selected edges.
2
FOURTH Load a Capture register every 4 selected edges.
3
EIGHTH Load a Capture register every 8 selected edges.
4
SIXTEENTH Load a Capture register every 16 selected edges.
Bits 19:18 – LDRB[1:0] RB Loading Edge Selection
Value Name Description
0
NONE None
1
RISING Rising edge of TIOAx
2
FALLING Falling edge of TIOAx
3
EDGE Each edge of TIOAx
Bits 17:16 – LDRA[1:0] RA Loading Edge Selection
Value Name Description
0
NONE None
1
RISING Rising edge of TIOAx
2
FALLING Falling edge of TIOAx
3
EDGE Each edge of TIOAx
Bit 15 – WAVE W
aveform Mode
Value Description
0
Capture mode is enabled.
1
Capture mode is disabled (Waveform mode is enabled).
SAM E70/S70/V70/V71 Family
T
imer Counter (TC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1519