Datasheet

Figure 50-21. Quadrature Error Detection
Peripheral Clock
MAXFILT = 2
PHA
PHB
A
bnormally formatted optical disk strips (theoretical view)
PHA
PHB
strip edge inaccuracy due to disk etching/printing process
resulting PHA, PHB electrical waveforms
PHA
PHB
Even with an abnormally formatted disk, there is no occurrence of PHA, PHB switching at the same time.
QERR
duration < MAXFILT
MAXFILT must be tuned according to several factors such as the peripheral clock frequency, type of rotary sensor
and rotation speed to be achieved.
50.6.16.4 Position and Rotation Measurement
When TC_BMR.POSEN is set, the motor axis position is processed on channel 0 (by means of the PHA, PHB edge
detections) and the number of motor revolutions are recorded on channel 1 if the IDX signal is provided on the TIOB1
input. If no IDX signal is available, the internal counter can be cleared for each revolution if the number of counts per
revolution is configured in TC_RC0.RC and the TC_CMR.CPCTRG bit is written to ‘1’. The position measurement
can be read in the TC_CV0 register and the rotation measurement can be read in the TC_CV1 register
.
Channel 0 and 1 must be configured in Capture mode (TC_CMR0.WAVE = 0). ‘Rising edge’ must be selected as the
External Trigger Edge (TC_CMR.ETRGEDG = 0x01) and ‘TIOAx’ must be selected as the External Trigger
(TC_CMR.ABETRG = 0x1). The process must be started by configuring TC_CCR.CLKEN and TC_CCR.SWTRG.
In parallel, the number of edges are accumulated on TC channel 0 and can be read on the TC_CV0 register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word.
The TC channel 0 is cleared for each increment of IDX count value.
Depending on the quadrature signals, the direction is decoded and allows to count up or down in TC channels 0 and
1. The direction status is reported on TC_QISR.
50.6.16.5 Speed Measurement
When TC_BMR.SPEEDEN is set, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register
. Channel 2 must be configured in
Waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter by
comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOAx output.
SAM E70/S70/V70/V71 Family
T
imer Counter (TC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1510