Datasheet

When DMA is used (on channel 0), the Register AB (TC_RAB) address must be configured as source address of the
transfer
. TC_RAB provides the next unread value from TC_RA and TC_RB. It may be read by the DMA after a
request has been triggered upon loading TC_RA or TC_RB.
50.6.9 Transfer with DMAC in Capture Mode
The DMAC can perform access from the TC to system memory in Capture mode only.
The following figure illustrates how TC_RA and TC_RB can be loaded in the system memory without processor
intervention.
Figure 50-5. Example of Transfer with DMAC in Capture Mode
TIOB
TIOA
RA
RB
Transfer to System Memory
Internal Peripheral Trigger
RA RB RA RB
T1,T2,T3,T4 = System Bus load dependent (t
min
= 8 Peripheral Clocks)
T1
T2
T3 T4
ETRGEDG = 1, LDRA = 1, LDRB = 2, ABETRG = 0
ETRGEDG = 3, LDRA = 3, LDRB = 0, ABETRG = 0
TIOB
TIOA
RA
Transfer to System Memory RA RA
T1,T2,T3,T4 = System Bus load dependent (t
min
= 8 Peripheral Clocks)
T1
T2
T3 T4
RA
RA
(when RA or RB loaded)
Internal Peripheral Trigger
(when RA loaded)
50.6.10 Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
The ABETRG bit in the TC_CMR selects TIOAx or TIOBx input signal as an external trigger or the trigger signal from
the output comparator of the PWM module. The External Trigger Edge Selection parameter (ETRGEDG field in
TC_CMR) defines the edge (rising, falling, or both) detected to generate an external trigger. If ETRGEDG = 0 (none),
the external trigger is disabled.
SAM E70/S70/V70/V71 Family
T
imer Counter (TC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1497