Datasheet

50.3 Block Diagram
Table 50-1. Timer Counter Clock Assignment
Name Definition
TIMER_CLOCK1 PCK6 or PCK7 (TC0 only)
TIMER_CLOCK2 MCK/8
TIMER_CLOCK3 MCK/32
TIMER_CLOCK4 MCK/128
TIMER_CLOCK5
(1)
SLCK
1. When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Master Clock register), SLCK input is
equivalent to Peripheral Clock.
2.
The PCK6 or PCK7 (TC0 only) frequency must be at least three times lower than peripheral clock frequency.
Figure 50-1. Timer Counter Block Diagram
Timer Counter
Channel 0
Timer Counter
Channel 1
Timer Counter
Channel 2
SYNC
Parallel I/O
Controller
TC1XC1S
TC0XC0S
TC2XC2S
INT0
INT1
INT2
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
Interrupt
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
SYNC
SYNC
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
TIMER_CLOCK1
FAULT
PWM
Note:
The QDEC connections are detailed in Predefined Connection of the Quadrature Decoder with T
imer Counters.
Table 50-2. Channel Signal Description
Signal Name Description
XC0, XC1, XC2 External Clock Inputs
TIOAx Capture Mode: Timer Counter Input
W
aveform Mode: Timer Counter Output
SAM E70/S70/V70/V71 Family
T
imer Counter (TC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1492