Datasheet

49.6.36 MCAN Tx FIFO/Queue Status
Name: MCAN_TXFQS
Offset: 0xC4
Reset: 0x00000000
Property: Read-only
The Tx FIFO/Queue status is related to the pending Tx requests listed in register MCAN_TXBRP. Therefore the effect
of Add/Cancellation requests may be delayed due to a running Tx scan (MCAN_TXBRP not yet updated).
In case of mixed configurations where dedicated Tx Buf
fers are combined with a Tx FIFO or a Tx Queue, the Put and
Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.
Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the
fourth buffer of the Tx FIFO.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
TFQF TFQPI[4:0]
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TFGI[4:0]
Access
R R R R R
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TFFL[5:0]
Access
R R R R R R
Reset 0 0 0 0 0 0
Bit 21 – TFQF Tx FIFO/Queue Full
Value Description
0
Tx FIFO/Queue not full.
1
Tx FIFO/Queue full.
Bits 20:16 – TFQPI[4:0] Tx FIFO/Queue Put Index
Tx FIFO/Queue write index pointer
, range 0 to 31.
Bits 12:8 – TFGI[4:0] Tx FIFO Get Index
Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured
(MCAN_TXBC.TFQM = ‘1’).
Bits 5:0 – TFFL[5:0] Tx FIFO Free Level
Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue
operation is configured (MCAN_TXBC.TFQM = ‘1’).
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1479