Datasheet

49.6.34 MCAN Receive Buffer / FIFO Element Size Configuration
Name: MCAN_RXESC
Offset: 0xBC
Reset: 0x00000000
Property: Read/Write
This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
Configures the number of data bytes belonging to a Receive Buf
fer / Receive FIFO element. Data field sizes >8 bytes
are intended for CAN FD operation only.
In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Receive
Buffer or Receive FIFO, only the number of bytes as configured by MCAN_RXESC are stored to the Receive Buffer
resp. Receive FIFO element. The rest of the frame’s data field is ignored.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
RBDS[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
F1DS[2:0] F0DS[2:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 10:8 – RBDS[2:0] Receive Buf
fer Data Field Size
Value Name Description
0
8_BYTE 8-byte data field
1
12_BYTE 12-byte data field
2
16_BYTE 16-byte data field
3
20_BYTE 20-byte data field
4
24_BYTE 24-byte data field
5
32_BYTE 32-byte data field
6
48_BYTE 48-byte data field
7
64_BYTE 64-byte data field
Bits 6:4 – F1DS[2:0] Receive FIFO 1 Data Field Size
Value Name Description
0
8_BYTE 8-byte data field
1
12_BYTE 12-byte data field
2
16_BYTE 16-byte data field
3
20_BYTE 20-byte data field
4
24_BYTE 24-byte data field
5
32_BYTE 32-byte data field
6
48_BYTE 48-byte data field
7
64_BYTE 64-byte data field
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1476