Datasheet

Bit 24 – EW W
arning Status
Value Description
0
Error_Warning status unchanged.
1
Error_Warning status changed.
Bit 23 – EP Error Passive
Value Description
0
Error_Passive status unchanged.
1
Error_Passive status changed.
Bit 22 – ELO Error Logging Overflow
Value Description
0
CAN Error Logging Counter did not overflow.
1
Overflow of CAN Error Logging Counter occurred.
Bit 19 – DRX Message stored to Dedicated Receive Buf
fer
The flag is set whenever a received message has been stored into a dedicated Receive Buffer.
Value Description
0
No Receive Buffer updated.
1
At least one received message stored into a Receive Buffer.
Bit 18 – TOO T
imeout Occurred
Value Description
0
No timeout.
1
Timeout reached.
Bit 17 – MRAF Message RAM Access Failure
The flag is set, when the Rx Handler
• has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following
message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler
starts processing of the following message.
• was not able to write a message to the Message RAM. In this case message storage is aborted.
In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Receive Buf
fer is not set, a
partly stored message is overwritten when the next message is stored to this location.
The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case
message transmission is aborted. In case of a Tx Handler access failure the MCAN is switched into Restricted
Operation mode (see Restricted Operation Mode). To leave Restricted Operation mode, the processor has to reset
MCAN_CCCR.ASM.
Value Description
0
No Message RAM access failure occurred.
1
Message RAM access failure occurred.
Bit 16 – TSW T
imestamp Wraparound
Value Description
0
No timestamp counter wrap-around.
1
Timestamp counter wrapped around.
Bit 15 – TEFL Tx Event FIFO Element Lost
Value Description
0
No Tx Event FIFO element lost.
1
Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.
Bit 14 – TEFF Tx Event FIFO Full
Value Description
0
Tx Event FIFO not full.
1
Tx Event FIFO full.
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1454