Datasheet

22.5.1 EEFC Flash Mode Register
Name: EEFC_FMR
Offset: 0x00
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the “EEFC W
rite Protection Mode Register” .
Bit 31 30 29 28 27 26 25 24
CLOE
Access
Reset
Bit 23 22 21 20 19 18 17 16
SCOD
Access
Reset
Bit 15 14 13 12 11 10 9 8
FWS[3:0]
Access
Reset
Bit 7 6 5 4 3 2 1 0
FRDY
Access
Reset
Bit 26 – CLOE Code Loop Optimization Enable
No Flash read should be done during change of this field.
Value Description
0
The opcode loop optimization is disabled.
1
The opcode loop optimization is enabled.
Bit 16 – SCOD Sequential Code Optimization Disable
No Flash read should be done during change of this field.
Value Description
0
The sequential code optimization is enabled.
1
The sequential code optimization is disabled.
Bits 11:8 – FWS[3:0] Flash W
ait State
This field defines the number of wait states for read and write operations:
FWS = Number of cycles for Read/Write operations - 1
Bit 0 – FRDY Flash Ready Interrupt Enable
Value Description
0
Flash ready does not generate an interrupt.
1
Flash ready (to accept a new command) generates an interrupt.
SAM E70/S70/V70/V71 Family
Enhanced Embedded Flash Controller (EEFC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 145