Datasheet

49.6.10 MCAN Timestamp Counter Value Register
Name: MCAN_TSCV
Offset: 0x24
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
TSC[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TSC[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:0 – TSC[15:0] T
imestamp Counter (cleared on write)
The internal/external Timestamp Counter value is captured on start of frame (both Receive and Transmit). When
MCAN_TSCC.TSS = 1, the Timestamp Counter is incremented in multiples of CAN bit times [ 1…16 ] depending on
the configuration of MCAN_TSCC.TCP. A wrap around sets interrupt flag MCAN_IR.TSW. Write access resets the
counter to zero.
When MCAN_TSCC.TSS = 2, TSC reflects the external Timestamp Counter value. Thus a write access has no
impact.
Note: A “wrap around” is a change of the Timestamp Counter value from non-zero to zero not caused by write
access to MCAN_TSCV.
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1446