Datasheet

Note: During the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual
plane.
One error can be detected in EEFC_FSR after this sequence:
•
Command Error: A bad keyword has been written in EEFC_FCR.
The sequence to write the user signature area is the following:
1. Write the full page, at any page address, within the internal memory area address space.
2. Execute the ‘Write User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field
EEFC_FCR.FARG is meaningless.
3. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting
the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated.
Two errors can be detected in EEFC_FSR after this sequence:
• Command Error: A bad keyword has been written in EEFC_FCR.
• Flash Error: At the end of the programming, the WriteVerify test of the Flash memory has failed.
The sequence to erase the user signature area is the following:
1. Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command. Field
EEFC_FCR.FARG is meaningless.
2. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting
the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated.
Two errors can be detected in EEFC_FSR after this sequence:
• Command Error: A bad keyword has been written in EEFC_FCR.
• Flash Error: At the end of the programming, the EraseVerify test of the Flash memory has failed.
22.4.3.10 ECC Errors and Corrections
The Flash embeds an ECC module able to correct one unique error and able to detect two errors. The errors are
detected while a read access is performed into memory array and stored in EEFC_FSR (see “EEFC Flash Status
Register”). The error report is kept until EEFC_FSR is read.
There is one flag for a unique error on lower half part of the Flash word (64 LSB) and one flag for the upper half part
(MSB). The multiple errors are reported in the same way.
Due to the anticipation technique to improve bandwidth throughput on instruction fetch, a reported error can be
located in the next sequential Flash word compared to the location of the instruction being executed, which is located
in the previously fetched Flash word.
If a software routine processes the error detection independently from the main software routine, the entire Flash
located software must be rewritten because there is no storage of the error location.
If only a software routine is running to program and check pages by reading EEFC_FSR, the situation differs from the
previous case. Performing a check for ECC unique errors just after page programming completion involves a read of
the newly programmed page. This read sequence is viewed as data accesses and is not optimized by the Flash
controller. Thus, in case of unique error, only the current page must be reprogrammed.
22.4.4 Register Write Protection
To prevent any single software error from corrupting EEFC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the “EEFC Write Protection Mode Register” (EEFC_WPMR).
The following register can be write-protected:
• “EEFC Flash Mode Register”
SAM E70/S70/V70/V71 Family
Enhanced Embedded Flash Controller (EEFC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 143