Datasheet

New transmit messages have to be written to the Tx FIFO starting with the Tx Buffer referenced by the Put Index
MCAN_TXFQS.TFQPI. An Add Request increments the Put Index to the next free Tx FIFO element. When the Put
Index reaches the Get Index, Tx FIFO Full (MCAN_TXFQS.TFQF = ‘1’) is signalled. In this case no further messages
should be written to the Tx FIFO until the next message has been transmitted and the Get Index has been
incremented.
When a single message is added to the Tx FIFO, the transmission is requested by writing a ‘1’ to the TXBAR bit
related to the Tx Buf
fer referenced by the Tx FIFO’s Put Index.
When multiple (n) messages are added to the Tx FIFO, they are written to n consecutive Tx Buffers starting with the
Put Index. The transmissions are then requested via MCAN_TXBAR. The Put Index is then cyclically incremented by
n. The number of requested Tx buffers should not exceed the number of free Tx Buffers as indicated by the Tx FIFO
Free Level.
When a transmission request for the Tx Buffer referenced by the Get Index is cancelled, the Get Index is incremented
to the next Tx Buffer with pending transmission request and the Tx FIFO Free Level is recalculated. When
transmission cancellation is applied to any other Tx Buffer, the Get Index and the FIFO Free Level remain
unchanged.
A Tx FIFO element allocates Element Size 32-bit words in the Message RAM (see the table Table 49-6). Therefore
the start address of the next available (free) Tx FIFO Buffer is calculated by adding Tx FIFO/Queue Put Index
MCAN_TXFQS.TFQPI (0…31) × Element Size to the Tx Buffer Start Address MCAN_TXBC.TBSA.
49.5.5.4 Tx Queue
Tx Queue operation is configured by programming MCAN_TXBC.TFQM to ‘1’. Messages stored in the Tx Queue are
transmitted starting with the message with the lowest Message ID (highest priority). In case that multiple Queue
Buffers are configured with the same Message ID, the Queue Buffer with the lowest buffer number is transmitted first.
New messages have to be written to the Tx Buffer referenced by the Put Index MCAN_TXFQS.TFQPI. An Add
Request cyclically increments the Put Index to the next free Tx Buffer. In case that the Tx Queue is full
(MCAN_TXFQS.TFQF = ‘1’), the Put Index is not valid and no further message should be written to the Tx Queue
until at least one of the requested messages has been sent out or a pending transmission request has been
cancelled.
The application may use register MCAN_TXBRP instead of the Put Index and may place messages to any Tx Buffer
without pending transmission request.
A Tx Queue Buffer allocates Element Size 32-bit words in the Message RAM (see the table Tx Buffer / FIFO / Queue
Element Size). Therefore the start address of the next available (free) Tx Queue Buffer is calculated by adding Tx
FIFO/Queue Put Index MCAN_TXFQS.TFQPI (0…31) × Element Size to the Tx Buffer Start Address
MCAN_TXBC.TBSA.
49.5.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
In this case the Tx Buffers section in the Message RAM is subdivided into a set of dedicated Tx Buffers and a Tx
FIFO. The number of dedicated Tx Buffers is configured by MCAN_TXBC.NDTB. The number of Tx Buffers assigned
to the Tx FIFO is configured by MCAN_TXBC.TFQS. In case MCAN_TXBC.TFQS is programmed to zero, only
dedicated Tx Buffers are used.
Figure 49-10. Example of Mixed Configuration Dedicated Tx Buffers / Tx FIFO
ID3 ID15 ID8 ID24 ID4 ID2
0123456789
Dedicated Tx Buffers Tx FIFO
.3.2.14..6.5
Get Index Put Index
Buffer Index
Tx Sequence
Tx prioritization:
•
Scan dedicated Tx Buffers and oldest pending Tx FIFO Buffer (referenced by MCAN_TXFS.TFGI)
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1421