Datasheet

When an Rx FIFO is operated in Overwrite mode and an Rx FIFO full condition is signalled, reading of the Rx FIFO
elements should start at least at get index + 1. The reason for that is, that it might happen, that a received message
is written to the Message RAM (put index) while the processor is reading from the Message RAM (get index). In this
case inconsistent data may be read from the respective Rx FIFO element. Adding an of
fset to the get index when
reading from the Rx FIFO avoids this problem. The offset depends on how fast the processor accesses the Rx FIFO.
The figure below shows an offset of two with respect to the get index when reading the Rx FIFO. In this case the two
messages stored in element 1 and 2 are lost.
Figure 49-8. Rx FIFO Overflow Handling
0
1
2
34
5
6
Rx FIFO Full
MCAN_RXFnS.FnPI
7
= MCAN_RXFnS.FnGI
0
1
2
34
5
6
Rx FIFO Overwrite
MCAN_RXFnS.FnPI
7
= MCAN_RXFnS.FnGI
element 0 overwritten
read Get Index + 2
(MCAN_RXFnS.FnF
= ‘1’)
(MCAN_RXFnS.FnF = ‘1’)
After reading from the Rx FIFO, the number of the last element read has to be written to the Rx FIFO Acknowledge
Index MCAN_RXFnA.FnA. This increments the get index to that element number. In case the put index has not been
incremented to this Rx FIFO element, the Rx FIFO full condition is reset (MCAN_RXFnS.FnF = ‘0’).
49.5.4.3 Dedicated Rx Buffers
The MCAN supports up to 64 dedicated Rx Buffers. The start address of the dedicated Rx Buffer section is
configured via MCAN_RXBC.RBSA.
For each Rx Buffer, a Standard or Extended Message ID Filter Element with SFEC / EFEC = 7 and SFID2 /
EFID2[10:9] = 0 has to be configured.
After a received message has been accepted by a filter element, the message is stored into the Rx Buffer in the
Message RAM referenced by the filter element. The format is the same as for an Rx FIFO element. In addition, the
flag MCAN_IR.DRX (Message stored in dedicated Rx Buffer) in MCAN_IR is set.
Table 49-3. Example Filter Configuration for Rx Buffers
Filter
Element
SFID1[10:0]
EFID1[28:0]
SFID2[10:9]
EFID2[10:9]
SFID2[5:0]
EFID2[5:0]
0 ID message 1 0 0
1 ID message 2 0 1
2 ID message 3 0 2
After the last word of a matching received message has been written to the Message RAM, the respective New Data
flag in the New Data 1 register (MCAN_NDAT1) and New Data 2 register (MCAN_NDAT2) is set. As long as the New
Data flag is set, the respective Rx Buffer is locked against updates from received matching frames. The New Data
flags have to be reset by the processor by writing a ‘1’ to the respective bit position.
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1417