Datasheet

Figure 49-6. Extended Message ID Filter Path
valid frame received
11 / 29 bit identifier
remote frame
29 bit
reject remote frames
discard frame
match filter element #0
match filter element #MCAN_XIDFC.LSE
yes
no
accept non-matching frames
acceptance / rejection
accept
reject
receive filter list enabled
MCAN_XIDFC.LSE[6:0] > 0
MCAN_GFC.ANFE[1] = ‘0’
MCAN_GFC.RRFE = ‘1’
MCAN_GFC.RRFE = ‘0’
11 bit
MCAN_XIDFC.LSE[6:0] = 0
MCAN_GFC.ANFE[1] = ‘1’
no
yes
no
yes
yes
no
store frame
FIFO selected and
no target FIFO full (blocking)
49.5.4.2 Rx FIFOs
Rx FIFO 0 and Rx FIFO 1 can be configured to hold up to 64 elements each. Configuration of the two Rx FIFOs is
done via the Rx FIFO 0 Configuration register (MCAN_RXF0C) and the Rx FIFO 1 Configuration register
(MCAN_RXF1C).
Received messages that passed acceptance filtering are transferred to the Rx FIFO as configured by the matching
filter element. For a description of the filter mechanisms available for Rx FIFO 0 and Rx FIFO 1, see Acceptance
Filtering. The Rx FIFO element is described in Rx Buf
fer and FIFO Element.
To avoid an Rx FIFO overflow, the Rx FIFO watermark can be used. When the Rx FIFO fill level reaches the Rx FIFO
watermark configured by MCAN_RXFnC.FnWM, interrupt flag MCAN_IR.RFnW is set. When the Rx FIFO Put Index
reaches the Rx FIFO Get Index, an Rx FIFO Full condition is signalled by MCAN_RXFnS.FnF. In addition, the
interrupt flag MCAN_IR.RFnF is set.
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1415