Datasheet

actual counter value can be read from MCAN_TOCV.TOC. The Timeout Counter can only be started while
MCAN_CCCR.INIT = ‘0’. It is stopped when MCAN_CCCR.INIT = ‘1’, e.g. when the MCAN enters Bus_Of
f state.
The operating mode is selected by MCAN_TOCC.TOS. When operating in Continuous mode, the counter starts when
MCAN_CCCR.INIT is reset. A write to MCAN_TOCV presets the counter to the value configured by
MCAN_TOCC.TOP and continues down-counting.
When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value
configured by MCAN_TOCC.TOP. Down-counting is started when the first FIFO element is stored. Writing to
MCAN_TOCV has no effect.
When the counter reaches zero, interrupt flag MCAN_IR.TOO is set. In Continuous mode, the counter is immediately
restarted at MCAN_TOCC.TOP.
Note: The clock signal for the Timeout Counter is derived from the CAN Core’s sample point signal. Therefore the
point in time where the Timeout Counter is decremented may vary due to the synchronization / re-synchronization
mechanism of the CAN Core. If the bit rate switch feature in CAN FD is used, the timeout counter is clocked
differently in arbitration and data field.
49.5.4 Rx Handling
The Rx Handler controls the acceptance filtering, the transfer of received messages to the Rx Buffers or to one of the
two Rx FIFOs, as well as the Rx FIFO’s Put and Get Indices.
49.5.4.1 Acceptance Filtering
The MCAN offers the possibility to configure two sets of acceptance filters, one for standard identifiers and one for
extended identifiers. These filters can be assigned to an Rx Buffer or to Rx FIFO 0,1. For acceptance filtering each
list of filters is executed from element #0 until the first matching element. Acceptance filtering stops at the first
matching element. The following filter elements are not evaluated for this message.
The main features are:
• Each filter element can be configured as
– range filter (from - to)
– filter for one or two dedicated IDs
– classic bit mask filter
• Each filter element is configurable for acceptance or rejection filtering
• Each filter element can be enabled / disabled individually
• Filters are checked sequentially, execution stops with the first matching filter element
Related configuration registers are:
• Global Filter Configuration (MCAN_GFC)
• Standard ID Filter Configuration (MCAN_SIDFC)
• Extended ID Filter Configuration (MCAN_XIDFC)
• Extended ID and Mask (MCAN_XIDAM)
Depending on the configuration of the filter element (SFEC/EFEC) a match triggers one of the following actions:
• Store received frame in FIFO 0 or FIFO 1
• Store received frame in Rx Buffer
• Store received frame in Rx Buffer and generate pulse at filter event pin
• Reject received frame
• Set High Priority Message interrupt flag (MCAN_IR.HPM)
• Set High Priority Message interrupt flag (MCAN_IR.HPM) and store received frame in FIFO 0 or FIFO 1
Acceptance filtering is started after the complete identifier has been received. After acceptance filtering has
completed, and if a matching Rx Buffer or Rx FIFO has been found, the Message Handler starts writing the received
message data in portions of 32 bit to the matching Rx Buffer or Rx FIFO. If the CAN protocol controller has detected
an error condition (e.g. CRC error), this message is discarded with the following impact on the effected Rx Buffer or
Rx FIFO:
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1412