Datasheet

timing and it can drive constant dominant or recessive values. The actual value at pin CANRX can be read from
MCAN_TEST
.RX. Both functions can be used to check the CAN bus’ physical layer.
Due to the synchronization mechanism between CAN clock and system bus clock domain, there may be a delay of
several system bus clock periods between writing to MCAN_TEST.TX until the new configuration is visible at output
pin CANTX. This applies also when reading input pin CANRX via MCAN_TEST.RX.
Note: Test modes should be used for production tests or self-test only. The software control for pin CANTX
interferes with all CAN protocol functions. It is not recommended to use test modes for application.
49.5.1.9.1 External Loop Back Mode
The MCAN can be set in External Loop Back mode by setting the bit MCAN_TEST.LBCK. In Loop Back mode, the
MCAN treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering)
into an Rx Buffer or an Rx FIFO. The figure below shows the connection of signals CANTX and CANRX to the MCAN
in External Loop Back mode.
This mode is provided for hardware self-test. To be independent from external stimulation, the MCAN ignores
acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop Back mode. In
this mode, the MCAN performs an internal feedback from its Tx output to its Rx input. The actual value of the CANRX
input pin is disregarded by the MCAN. The transmitted messages can be monitored at the CANTX pin.
49.5.1.9.2 Internal Loop Back Mode
Internal Loop Back mode is entered by setting bits MCAN_TEST.LBCK and MCAN_CCCR.MON. This mode can be
used for a “Hot Selftest”, meaning the MCAN can be tested without affecting a running CAN system connected to the
pins CANTX and CANRX. In this mode, pin CANRX is disconnected from the MCAN, and pin CANTX is held
recessive. The figure below shows the connection of CANTX and CANRX to the MCAN when Internal Loop Back
mode is enabled.
Figure 49-4. Pin Control in Loop Back Modes
External Loop Back Mode Internal Loop Back Mode
Tx Rx
MCAN
•
•
CANRXCANTX
Tx Rx
MCAN
•
•
=1
CANRXCANTX
49.5.2 Timestamp Generation
For timestamp generation the MCAN supplies a 16-bit wrap-around counter. A prescaler TSCC.TCP can be
configured to clock the counter in multiples of CAN bit times (1…16). The counter is readable via MCAN_TSCV
.TSC.
A write access to the Timestamp Counter Value register (MCAN_TSCV) resets the counter to zero. When the
timestamp counter wraps around, interrupt flag MCAN_IR.TSW is set.
On start of frame reception / transmission the counter value is captured and stored into the timestamp section of an
Rx Buffer / Rx FIFO (RXTS[15:0]) or Tx Event FIFO (TXTS[15:0]) element.
By programming bit MCAN_TSCC.TSS an external 16-bit timestamp can be used. See Timestamping for more
details.
49.5.3 Timeout Counter
To signal timeout conditions for Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO, the MCAN supplies a 16-bit Timeout
Counter
. It operates as down-counter and uses the same prescaler controlled by TSCC.TCP as the Timestamp
Counter. The Timeout Counter is configured via the Timeout Counter Configuration register (MCAN_TOCC). The
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1411