Datasheet

Table 49-1. Coding of DLC in CAN FD
DLC 9 10 11 12 13 14 15
Number of Data Bytes 12 16 20 24 32 48 64
In CAN FD frames, the bit timing will be switched inside the frame, after the BRS (Bit Rate Switch) bit, if this bit is
recessive. Before the BRS bit, in the CAN FD arbitration phase, the
nominal CAN bit timing is used as defined by the
Nominal Bit Timing and Prescaler register (MCAN_NBTP). In the following CAN FD data phase, the data phase CAN
bit timing is used as defined by the Data Bit Timing and Prescaler register (MCAN_DBTP). The bit timing reverts back
from the data phase timing at the CRC delimiter or when an error is detected, whichever occurs first.
The maximum configurable bit rate in the CAN FD data phase depends on the CAN core clock frequency. Example:
with a CAN clock frequency of 20 MHz and the shortest configurable bit time of 4 t
q
, the bit rate in the data phase is 5
Mbit/s.
In both data frame formats, CAN FD and CAN FD with bit rate switching, the value of the bit ESI (Error Status
Indicator) is determined by the transmitter’s error state at the start of the transmission. If the transmitter is error
passive, ESI is transmitted recessive, else it is transmitted dominant.
49.5.1.4 Transmitter Delay Compensation
During the data phase of a CAN FD transmission only one node is transmitting, all others are receivers. The length of
the bus line has no impact. When transmitting via pin CANTX the protocol controller receives the transmitted data
from its local CAN transceiver via pin CANRX. The received data is delayed by the transmitter delay. In case this
delay is greater than TSEG1 (time segment before sample point), a bit error is detected. In order to enable a data
phase bit time that is even shorter than the transmitter delay, the delay compensation is introduced. Without delay
compensation, the bit rate in the data phase of a CAN FD frame is limited by the delay.
49.5.1.4.1 Description
The MCAN protocol unit has implemented a delay compensation mechanism to compensate the delay, thereby
enabling transmission with higher bit rates during the CAN FD data phase independent of the delay of a specific CAN
transceiver.
To check for bit errors during the data phase, the delayed transmit data is compared against the received data at the
secondary sample point. If a bit error is detected, the transmitter will react to this bit error at the next following regular
sample point. During arbitration phase the delay compensation is always disabled.
The transmitter delay compensation enables configurations where the data bit time is shorter than the transmitter
delay, it is described in detail in the new ISO11898-1. It is enabled by setting bit MCAN_DBTP.TDC.
The received bit is compared against the transmitted bit at the SSP. The SSP position is defined as the sum of the
measured delay from the MCAN’s transmit output CANTX through the transceiver to the receive input CANRX plus
the transmitter delay compensation offset as configured by MCAN_TDCR.TDCO. The transmitter delay
compensation offset is used to adjust the position of the SSP inside the received bit (e.g. half of the bit time in the
data phase). The position of the secondary sample point is rounded down to the next integer number of CAN core
clock periods.
MCAN_PSR.TDCV shows the actual transmitter delay compensation value. MCAN_PSR.TDCV is cleared when
MCAN_CCCR.INIT is set and is updated at each transmission of an FD frame while MCAN_DBTP.TDC is set.
The following boundary conditions have to be considered for the delay compensation implemented in the MCAN:
• The sum of the measured delay from CANTX to CANRX and the configured delay compensation offset
MCAN_TDCR.TDCO has to be less than 6 bit times in the data phase.
• The sum of the measured delay from CANTX to CANRX and the configured delay compensation offset
MCAN_TDCR.TDCO has to be less or equal 127 CAN core clock periods. In case this sum exceeds 127 CAN
core clock periods, the maximum value of 127 CAN core clock periods is used for delay compensation.
• The data phase ends at the sample point of the CRC delimiter, that stops checking of receive bits at the SSPs.
49.5.1.4.2 Transmitter Delay Measurement
If transmitter delay compensation is enabled by programming MCAN_DBTP.TDC = ‘1’, the measurement is started
within each transmitted CAN FD frame at the falling edge of bit FDF to bit res. The measurement is stopped when
this edge is seen at the receive input CANRX of the transmitter.
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1408