Datasheet

49.4.4 Address Configuration
The LSBs [bits 15:2] for each section of the CAN Message RAM are configured in the respective buffer configuration
registers as detailed in Message RAM.
The MSBs [bits 31:16] of the CAN Message RAM for CAN0 and CAN1 are configured in CCFG_CAN0 and
CCFG_SYSIO registers.
49.4.5 Timestamping
Timestamping uses the value of CV in the TC Counter Value 0 register (TC_CV0) at address 0x4000C010. TC0 can
use the programmable clocks PCK6 or PCK7 as input. Refer to the section “T
imer Counter (TC)” for more details.
The selection between PCK6 and PCK7 is done in the Matrix Peripheral Clock Configuration Register
(CCFG_PCCR), using the bit TC0CC. Refer to this register in the section “Bus Matrix (MATRIX)” for more details.
These clocks can be programmed in the the registers PMC Programmable Clock Registers PMC_PCK6 and
PMC_PCK7, respectively. Refer to these registers in the section “Power Management Controller (PMC)” for more
details.
Related Links
50. Timer Counter (TC)
31. Power Management Controller (PMC)
49.5 Functional Description
49.5.1 Operating Modes
49.5.1.1 Software Initialization
Software initialization is started by setting bit MCAN_CCCR.INIT, either by software or by a hardware reset, when an
uncorrected bit error was detected in the Message RAM, or by going Bus_Of
f. While MCAN_CCCR.INIT is set,
message transfer from and to the CAN bus is stopped and the status of the CAN bus output CANTX is recessive
(HIGH). The counters of the Error Management Logic EML are unchanged. Setting MCAN_CCCR.INIT does not
change any configuration register. Resetting MCAN_CCCR.INIT finishes the software initialization. Afterwards the Bit
Stream Processor BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a
sequence of 11 consecutive recessive bits (≡ Bus_Idle) before it can take part in bus activities and start the message
transfer.
Access to the MCAN configuration registers is only enabled when both bits MCAN_CCCR.INIT and
MCAN_CCCR.CCE are set (protected write).
MCAN_CCCR.CCE can only be configured when MCAN_CCCR.INIT = ‘1’. MCAN_CCCR.CCE is automatically
cleared when MCAN_CCCR.INIT = ‘0’.
The following registers are cleared when MCAN_CCCR.CCE = ‘1’:
• High Priority Message Status (MCAN_HPMS)
• Receive FIFO 0 Status (MCAN_RXF0S)
• Receive FIFO 1 Status (MCAN_RXF1S)
• Transmit FIFO/Queue Status (MCAN_TXFQS)
• Transmit Buffer Request Pending (MCAN_TXBRP)
• Transmit Buffer Transmission Occurred (MCAN_TXBTO)
• Transmit Buffer Cancellation Finished (MCAN_TXBCF)
• Transmit Event FIFO Status (MCAN_TXEFS)
The Timeout Counter value MCAN_TOCV.TOC is loaded with the value configured by MCAN_TOCC.TOP when
MCAN_CCCR.CCE = ‘1’.
In addition, the state machines of the Tx Handler and Rx Handler are held in idle state while MCAN_CCCR.CCE =
‘1’.
The following registers are only writeable while MCAN_CCCR.CCE = ‘0’
SAM E70/S70/V70/V71 Family
Controller Area Network (MCAN)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1406