Datasheet

48.7.28 AHB Channel Mask 0 Register
Name: MLB_ACMR0
Offset: 0x3D8
Reset: 0x00000000
Property: Read/Write
Using the AHB Channel Mask (ACMRn) register, the HC can control which channel(s) generate interrupts on
ahb_int[1:0]. All ACMRn register bits default as ‘0’ (“masked”); therefore, the HC must initially write ACMRn to enable
interrupts. Each bit of ACMRn is read/write accessible.
Bit 31 30 29 28 27 26 25 24
CHM[31:24]
Access
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CHM[23:16]
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CHM[15:8]
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CHM[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – CHM[31:0] Bitwise Channel Mask Bits 31 to 0
CHM[n] = 1 indicates that channel n can generate an interrupt.
SAM E70/S70/V70/V71 Family
Media Local Bus (MLB)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1402