Datasheet

48.7.26 AHB Channel Status 0 Register
Name: MLB_ACSR0
Offset: 0x3D0
Reset: 0x00000000
Property: Read/Write
The AHB Channel Status (ACSRn) registers contain interrupt bits for each of the 64 physical channels. When an
MLB_ACSRn register bit is set, it indicates that the corresponding physical channel has an interrupt pending.
An AHB interrupt is triggered when either DNEn or ERRn is set within the AHB Channel Descriptor
. The HC is
notified of the channel interrupt via ahb_int[1:0]. When an interrupt occurs in MLB_ACSR0 (for channels 31 to 0)
MediaLB IRQ0 is set. When an interrupt occurs in MLB_ACSR1 (for channels 63 to 32) MediaLB IRQ1 is set.
Interrupts in MLB_ACSR0 and MLB_ACSR1 can be optionally multiplexed onto a single interrupt signal, MediaLB
IRQ0, if MLB_ACTL.SMX = 1. If MLB_ACTL.SCE = 0, hardware automatically clears the interrupt bit(s) after the HC
reads the ACSRn register. Alternatively, if MLB_ACTL.SCE = 1, software must write a 1 to the appropriate bit(s) of
MLB_ACSRn to clear the interrupt(s).
Bit 31 30 29 28 27 26 25 24
CHS: Interrupt Status for Logical Channels [31[31:24]
Access
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CHS: Interrupt Status for Logical Channels [31[23:16]
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CHS: Interrupt Status for Logical Channels [31[15:8]
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CHS: Interrupt Status for Logical Channels [31[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – CHS: Interrupt Status for Logical Channels [31[31:0] 0] (cleared by writing a 1)
CHS[n] = 1 indicates that an interrupt is pending on channel n.
SAM E70/S70/V70/V71 Family
Media Local Bus (MLB)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1400