Datasheet

Figure 22-9. Partial Page Programming
32 bits wide
32 bits wide
FF FF FF FF
FF
FF FF FF
FF FF FF FF
FF FF FF FF
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
Step 2: Flash array after programming
128-bit at address 0xX00 (write latch buffer + WP)
CA FE CA FE
CA FE CA FE
address space
for
Page N
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
Step 1: Flash array after page erase
C
A FE
C
A F
E
C
A FE
C
A F
E
32 bits wide
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
Step 3: Flash array after programming
a second 128-bit data at address 0xX10
(write latch buffer + WP)
CA FE CA FE
CA FE CA FE
FF FF FF FF
FF FF FF FF
FF FF FF FF
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
SAM E70/S70/V70/V71 Family
Enhanced Embedded Flash Controller (EEFC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 137