Datasheet

Figure 48-22. Single-packet Asynchronous or Control System Memory Structure
Non-Segmented Packets
Packet 1
(PG = 0)
Packet 2
(
PG = 1)
Packet 3
(
PG = 0)
Packet 4
(PG = 1)
PS1 = 1
PS2 = 1
PS1 = 1
PS2 = 1
BD1
BD2
BD1
BD2
BA1
BA2
BA1
BA2
Buffer 1
Buffer
2
Buffer 3
Buffer 4
Packet 5
(PG = 0)
Packet 5
continued
(PG = 1)
Packet 5
continued
(PG = 0)
(PG = 1)
PS1 = 1
PS2 = 0
PS1 = 0
PS2 = 1
BD1
BD2
BD1
BD2
BA1
BA2
BA1
BA2
Buffer 5
Buffer 6
Buffer 7
Buffer 8
Non-Segmented Packets
Table 48-23. Single-packet Asynchronous and Control Entry Format
Bit Offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CE LE PG Reserved
16 Reserved
32 RDY1 DNE1 ERR1 PS1 MEP1 BD1[10:0]
48 RDY2 DNE2 ERR2 PS2 MEP2 BD2[10:0]
64 BA1[15:0]
80 BA1[31:16]
96 BA2[15:0]
112 BA2[31:16]
Multiple-packet Mode
The multiple-packet mode asynchronous and control buf
fering scheme supports more than one packet per system
memory buffer, as shown in the following figure. Multiple- packet mode reduces the interrupt rate for packet channels
at the cost of increasing buffering and latency.
For Tx packet channels in multiple-packet mode, software sets the packet start bit (PSn) for every buffer. Setting PSn
informs hardware that the first two bytes of the buffer contains the port message length (PML) of the first packet. After
the first packet, hardware keeps track of where packets start and end within the current buffer. Software should not
write to PSn while the buffer is active (RDYn = 1 and DNEn = 0). For Tx packet channels, the buffer is done (DNEn=
1) when the last byte of the last packet in the buffer is read from system memory. Software should set the buffer
depth to contain the exact number of complete packets for that buffer. Segmented buffers are not supported for Tx
packet channels in multiple-packet mode.
SAM E70/S70/V70/V71 Family
Media Local Bus (MLB)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1364