Datasheet

Figure 48-20. Endianness Overview
MSB
LSB
LSB
MSB
32-bit Word
Byte 3 Byte 2 Byte 1 Byte 0
Big Endian
Little Endian
The following figure shows an example of the ping-pong system memory structure. This system memory structure is
similar for all channel types and shows the relationship between the BAn, BDn, and PG descriptor fields.
Figure 48-21. Ping-Pong System Memory Structure
Ping Buffer
(PG = 0)
Pong Buffer
(PG = 1)
BA1
BA2
BD1
BD2
4G - 1
Each ADT entry holds a 32-bit BAn field which defines the start of each ping or pong buffer within system memory.
The BDn field is used to indicate the size for the respective ping or pong page. The maximum size is 2k-entries for
asynchronous and control channels; 8k-entries for isochronous and synchronous channels.
AHB Synchronous Channel Descriptors
T
able 48-21 shows the format for a synchronous ADT entry. The field definitions are defined in Table 48-22. Each
synchronous channel buffer can be up to 8k-bytes deep.
Table 48-21. Synchronous ADT Entry Format
Bit Offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CE LE PG Reserved
16 Reserved
32 RDY1 DNE1 ERR1 BD1[12:0]
48 RDY2 DNE2 ERR2 BD2[12:0]
64 BA1[15:0]
80 BA1[31:16]
96 BA2[15:0]
112 BA2[31:16]
AHB Isochronous Channel Descriptors
The isochronous buf
fering scheme allows each ping or pong buffer to contain a single block or a multiple number of
blocks. For this reason, the isochronous buffer depth (BDn) must be defined in terms of an integer number (n) and
block size (BS) (e.g. BDn = n x (BS + 1) - 1).
Table 48-22 shows the format for an isochronous ADT entry. The field definitions are defined in Table 48-23. Each
isochronous channel buffer can be up to 8k-bytes deep.
SAM E70/S70/V70/V71 Family
Media Local Bus (MLB)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1362