Datasheet
The MIF block allows the HC to access the external Data Buffer RAM (DBR) directly when MLB_MADR.TB is set.
Any write to the MLB_MADR triggers a single read or write cycle. Reading from the MLB_MADR register does not
initiate read/write access.
Figure 48-19. MIF DBR Read and W
rite Flow Diagrams
Transfer
Complete?
Start
Write data to
MDAT
Write address &
control to MADR
Stop
MIF DBR Write:
Transfer
Complete?
Start
Write address &
control to MADR
Stop
MIF DBR Read:
Read data from
MDAT
MCTL.XCMP = 0
MCTL.XCMP = 1
MCTL.XCMP = 0
MCTL.XCMP = 1
Direct DBR Writes
For a direct write of the DBR, the HC first loads the 8-bit data entry into the MLB_MDA
T0 register at bits[7:0].
MLB_MDAT1–3 and MLB_MDWE0–3 are not used for DBR access.
After the MLB_MDAT0 register is set up, a write cycle is initiated by writing the address and control information to
MLB_MADR as follows:
• MLB_MADR.WNR = 1
• MLB_MADR.TB = 1
• MLB_MADR.ADDR[13:0] = 14-bit Target Address
The MIF block sets MLB_MCTL.XCMP = 1 to inform the HC when the write is complete.
Direct DBR Reads
For a direct read of the DBR, the HC initiates a read cycle by writing the address and control information to
MLB_MADR as follows:
• MLB_MADR.WNR = 0
• MLB_MADR.TB = 1
• MLB_MADR.ADDR[13:0] = 14-bit target address
The MIF block sets MLB_MCTL.XCMP = 1 to inform the HC when the read is complete. The HC can then read the 8-
bit data entry from the MLB_MDAT0 register at bits[7:0].
48.6.3.5 Interrupt Interface Block
The Interrupt Interface (INTIF) block performs a low-priority polling algorithm of each of the HBI channel descriptors.
The INTIF alerts the HBI block when specific changes to HBI Channel Descriptors occur.
• For asynchronous and control read/write channels:
– a packet is available to read in the channel buffer, or
– sufficient empty space is available in the channel buffer to accept a requested packet write.
• For isochronous read/write channels:
– the number of valid bytes in the channel buffer exceeds the block size, or
– the number of empty bytes in the channel buffer exceeds the block size.
SAM E70/S70/V70/V71 Family
Media Local Bus (MLB)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1359