Datasheet

Receive devices retain the write address pointer to the associated circular data buffer in the DBR, while transmit
devices retain the read address pointer
. The DMA controllers in the routing fabric are responsible for ensuring that
the circular buffers do not overflow or underflow. Each channel type (e.g., synchronous, isochronous, asynchronous
and control) has Full and Empty detection.
• Synchronous Channels
For synchronous channels, two mechanisms prevent overflow and underflow of the data buffer:
– Hardware aligns the read pointer (RPTR) to the write pointer (WPTR) to ensure an offset of two sub-
buffers.
– RPTR and WPTR are periodically synchronized to the start of the next sub-buffer (e.g. following a
FRAMESYNC).
• Isochronous Channels
For isochronous channels, hardware does not read from an empty data buffer or write to a full data buffer. The
conditions used by hardware for detection include:
Data buffer Empty condition: (RPTR = WPTR) AND (BF = 0), and
Data buffer Full condition: (WPTR = RPTR) AND (BF = 1).
• Asynchronous and Control Channels
For asynchronous and control channels, hardware does not read from an empty data buffer or write to a full data
buffer. Hardware evaluates the DMA pointers (RPTR, WPTR) and packet count (RPC, WPC) to detect the data
buffer condition, where:
– Data buffer Empty condition: (RPTR = WPTR) AND (RPC = WPC), and
– Data buffer Full condition: ((WPTR = RPTR) AND (WPC != RPC)) OR (WPC = (RPC - 1)).
Channel Table RAM
The MLB has an external Channel Table RAM (CTR) that is 128-bit x 144-entry. The CTR allows system software to
dynamically configure channel routing and allocate data buffers in the DBR.
The CTR is logically divided into three sub-tables:
• Channel Descriptor Table (CDT)
• AHB Descriptor Table (ADT)
• Channel Allocation Table (CAT)
Address Mapping
Table 48-10. CTR Address Mapping
Label Address Bits 127…96 Bits 95…64 Bits 63…32 Bits 31…0
Channel Descriptor Table (CDT):
CDT 0x00 CDT0[127:0], CL = 0
0x01 CDT1[127:0], CL = 1
0x02 CDT2[127:0], CL = 2
... ...
0x3D CDT61[127:0], CL = 61
0x3E CDT62[127:0], CL = 62
0x3F CDT63[127:0], CL = 63
AHB Descriptor Table (ADT):
SAM E70/S70/V70/V71 Family
Media Local Bus (MLB)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1350