Datasheet

47.6.1 UART Control Register
Name: UART_CR
Offset: 0x00
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
REQCLR RSTSTA
Access
W W
Reset – –
Bit 7 6 5 4 3 2 1 0
TXDIS TXEN RXDIS RXEN RSTTX RSTRX
Access
W W W W W W
Reset – – – – – –
Bit 12 – REQCLR Request Clear
•
SleepWalking enabled:
0: No effect.
1: Bit REQCLR clears the potential clock request currently issued by UART, thus the potential system wake-up is
cancelled.
• SleepWalking disabled:
0: No effect.
1: Bit REQCLR restarts the comparison trigger to enable receive holding register loading.
Bit 8 – RSTSTA Reset Status
Value Description
0
No effect.
1
Resets the status bits PARE, FRAME, CMP and OVRE in the UART_SR.
Bit 7 – TXDIS T
ransmitter Disable
Value Description
0
No effect.
1
The transmitter is disabled. If a character is being processed and a character has been written in the
UAR
T_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.
Bit 6 – TXEN T
ransmitter Enable
Value Description
0
No effect.
1
The transmitter is enabled if TXDIS is 0.
Bit 5 – RXDIS Receiver Disable
SAM E70/S70/V70/V71 Family
Universal Asynchronous Receiver T
ransmitter (UART)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1313