Datasheet

Figure 47-13. Asynchronous Event Generating Only Partial Wake-up
D0 D1 D7
D0
D1
D7
RHR = 0xF5,
VAL1/2 = 0xF5
=> match
=>
RHR = 0x85,
VAL1 = 0x00
=> no match
Case with VAL1 = VAL2 = 0x00, CMPPAR = Don’t care
RXD
PCLK_req
PCLK
(Main RC)
SystemWakeUp_req
Idle Start Parity Stop
Case with VAL1 = 0xF5, VAL2 = 0xF5, CMPPAR = 1
RXD
PCLK_req
PCLK
(Main RC)
SystemWakeUp_req
Idle Start Stop
Parity = NOK
DATA match
and Parity NOK
Related Links
31. Power Management Controller (PMC)
47.5.7 Register Write Protection
To prevent any single software error from corrupting UART behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the UAR
T Write Protection Mode Register (UART_WPMR).
The following registers can be write-protected:
• UART Mode Register
• UART Baud Rate Generator Register
• UART Comparison Register
47.5.8 Test Modes
The UART supports three test modes. These modes of operation are programmed by using the CHMODE field in
UART_MR.
The Automatic Echo mode allows a bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to
the UTXD line. The transmitter operates normally, but has no effect on the UTXD line.
The Local Loopback mode allows the transmitted characters to be received. UTXD and URXD pins are not used and
the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no effect and
the UTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver are
disabled and have no effect. This mode allows a bit-by-bit retransmission.
SAM E70/S70/V70/V71 Family
Universal Asynchronous Receiver T
ransmitter (UART)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1310