Datasheet

Figure 47-10. Transmitter Control
UART_THR
Shift Register
UTXD
TXRDY
TXEMPTY
Data 0 Data 1
Data 0
Data 0
Data 1
Dat
a 1S S PP
Write Data 0
in UART_THR
Write Data 1
in UART_THR
stop
stop
47.5.4 DMA Support
Both the receiver and the transmitter of the UART are connected to a DMA Controller (DMAC) channel.
The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface.
47.5.5 Comparison Function on Received Character
When a comparison is performed on a received character, the result of the comparison is reported on the CMP flag in
UAR
T_SR when UART_RHR is loaded with the new received character. The CMP flag is cleared by writing a one to
the RSTSTA bit in UART_CR.
UART_CMPR (see UART Comparison Register) can be programmed to provide different comparison methods.
These are listed below:
• If VAL1 equals VAL2, then the comparison is performed on a single value and the flag is set to 1 if the received
character equals VAL1.
• If VAL1 is strictly lower than VAL2, then any value between VAL1 and VAL2 sets the CMP flag.
• If VAL1 is strictly higher than VAL2, then the flag CMP is set to 1 if either received character equals VAL1 or
VAL2.
By programming the CMPMODE bit to 1, the comparison function result triggers the start of the loading of
UART_RHR (see the figure below). The trigger condition occurs as soon as the received character value matches the
condition defined by the programming of VAL1, VAL2 and CMPPAR in UART_CMPR. The comparison trigger event
can be restarted by writing a one to the REQCLR bit in UART_CR.
Figure 47-11. Receive Holding Register Management
RXD
0x0F
0x06
CMPMODE = 1, VAL1 = VAL2 = 0x06
RXRDY rising enabled
0xF0
0x08
0x06
Peripheral
Clo
ck
Write REQCLR
RDR
0x06 0xF0
0x06
RXRDY
0x08
0x
0F
SAM E70/S70/V70/V71 Family
Universal Asynchronous Receiver T
ransmitter (UART)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1307