Datasheet

47.5.2.7 Receiver Digital Filter
The UART embeds a digital filter on the receive line. It is disabled by default and can be enabled by writing a logical 1
in the FIL
TER bit of UART_MR. When enabled, the receive line is sampled using the 16x bit clock and a three-
sample filter (majority 2 over 3) determines the value of the line.
47.5.3 Transmitter
47.5.3.1 Transmitter Reset, Enable and Disable
After device reset, the UART transmitter is disabled and must be enabled before being used. The transmitter is
enabled by writing UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be
written in the Transmit Holding Register (UART_THR) before actually starting the transmission.
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the internal shift register and/or a
character has been written in the UART_THR, the characters are completed before the transmitter is actually
stopped.
The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1. This
immediately stops the transmitter, whether or not it is processing characters.
47.5.3.2 Transmit Format
The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the format
defined in UART_MR and the data stored in the internal shift register. One start bit at level 0, then the 8 data bits,
from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown
in the following figure. The field PARE in UART_MR defines whether or not a parity bit is shifted out. When a parity bit
is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
Figure 47-9. Character Transmission
D0 D1 D2 D3 D4 D5 D6 D7
UTXD
Start
Bit
Parity
Bit
Stop
Bit
Example: Parity enabled
Baud Rate
Clock
47.5.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in UART_SR. The transmission starts
when the programmer writes in the UAR
T_THR, and after the written character is transferred from UART_THR to the
internal shift register. The TXRDY bit remains high until a second character is written in UART_THR. As soon as the
first character is completed, the last character written in UART_THR is transferred into the internal shift register and
TXRDY rises again, showing that the holding register is empty.
When both the internal shift register and UART_THR are empty, i.e., all the characters written in UART_THR have
been processed, the TXEMPTY bit rises after the last stop bit has been completed.
SAM E70/S70/V70/V71 Family
Universal Asynchronous Receiver Transmitter (UART)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1306