Datasheet

Figure 47-5. Receiver Ready
D0 D1 D2 D3 D4 D5 D6 D7 PS
S
D0 D1 D2 D3 D4 D5 D6 D7 P
URXD
Read UART_RHR
RXRDY
47.5.2.4 Receiver Overrun
The OVRE status bit in UART_SR is set if UART_RHR has not been read by the software (or the DMA Controller)
since the last transfer
, the RXRDY bit is still set and a new character is received. OVRE is cleared when the software
writes a 1 to the bit RSTSTA (Reset Status) in UART_CR.
Figure 47-6. Receiver Overrun
D0 D1 D2 D3 D4 D5 D6 D7 PS
S
D0 D1 D2 D3 D4 D5 D6 D7 P
URXD
RSTST
A
RXRDY
OVRE
stop
stop
47.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the
field P
AR in the Mode Register (UART_MR). It then compares the result with the received parity bit. If different, the
parity error bit PARE in UART_SR is set at the same time RXRDY is set. The parity bit is cleared when UART_CR is
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.
Figure 47-7. Parity Error
stop
D0 D1 D2 D3 D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit
47.5.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UAR
T_SR is set at the same time
the RXRDY bit is set. The FRAME bit remains high until the Control Register (UART_CR) is written with the bit
RSTSTA at 1.
Figure 47-8. Receiver Framing Error
D0 D1 D2 D3 D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop
SAM E70/S70/V70/V71 Family
Universal Asynchronous Receiver T
ransmitter (UART)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1305