Datasheet

47.4 Product Dependencies
47.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Controller to
enable I/O line operations of the UAR
T.
47.4.2 Power Management
The UART clock can be controlled through the Power Management Controller (PMC). In this case, the user must first
configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
In SleepWalking mode (asynchronous partial wake-up), the PMC must be configured to enable SleepWalking for the
UART in the Sleepwalking Enable Register (PMC_SLPWK_ER). Depending on the instructions (requests) provided
by the UART to the PMC, the system clock may or may not be automatically provided to the UART.
47.4.3 Interrupt Sources
The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling
requires programming of the Interrupt Controller before configuring the UART.
47.5 Functional Description
The UART operates in Asynchronous mode only and supports only 8-bit character handling (with parity). It has no
clock pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features
are compatible with those of a standard USART.
47.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.
The baud rate clock is the peripheral clock divided by 16 times the clock divisor (CD) value written in the Baud Rate
Generator register (UART_BRGR). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains
inactive. The maximum allowable baud rate is peripheral clock orPMC PCK (PCK) divided by 16. The minimum
allowable baud rate is peripheral clock or PCK divided by (16 x 65536).The clock source driving the baud rate
generator (peripheral clock or PCK) can be selected by writing the bit BRSRCCK in UART_MR.
If PCK is selected, the baud rate is independent of the processor/bus clock. Thus the processor clock can be
changed while UART is enabled. The processor clock frequency changes must be performed only by programming
the field PRES in PMC_MCKR (see "Power Management Controller (PMC)"). Other methods to modify the
processor/bus clock frequency (PLL multiplier, etc.) are forbidden when UART is enabled.
The peripheral clock frequency must be at least three times higher than PCK.
Figure 47-2. Baud Rate Generator
peripheral clock
16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
Receiver
Sampling Cloc
k
PCKx
BRSRCCK
1
0
SAM E70/S70/V70/V71 Family
Universal Asynchronous Receiver T
ransmitter (UART)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1303