Datasheet

46.7.32 USART LIN Mode Register
Name: US_LINMR
Offset: 0x0054
Reset: 0x0
Property: Read/Write
This register is relevant only if USART_MODE = 0xA or 0xB in the USAR
T Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SYNCDIS PDCM
Access
Reset 0 0
Bit 15 14 13 12 11 10 9 8
DLC[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WKUPTYP FSDIS DLM CHKTYP CHKDIS PARDIS NACT[1:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 17 – SYNCDIS Synchronization Disable
Value Description
0
The synchronization procedure is performed in LIN slave node configuration.
1
The synchronization procedure is not performed in LIN slave node configuration.
Bit 16 – PDCM DMAC
Mode
Value Description
0
The LIN mode register US_LINMR is not written by the DMAC.
1
The LIN mode register US_LINMR (excepting that flag) is written by the DMAC.
Bits 15:8 – DLC[7:0] Data Length Control
Value Description
0–255
Defines the response data length if DLM = 0,in that case the response data length is equal to DLC+1
bytes.
Bit 7 – WKUPTYP W
akeup Signal Type
Value Description
0
Setting the bit LINWKUP in US_CR sends a LIN 2.0 wakeup signal.
1
Setting the bit LINWKUP in US_CR sends a LIN 1.3 wakeup signal.
Bit 6 – FSDIS Frame Slot Mode Disable
Value Description
0
The Frame Slot mode is enabled.
1
The Frame Slot mode is disabled.
Bit 5 – DLM Data Length Mode
Value Description
0
The response data length is defined by field DLC of this register.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1284