Datasheet

• Two 128-bit read buffers used for code read optimization
•
One 128-bit read buffer used for data read optimization
• One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is
write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final
address.
• Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated
with a lock region composed of several pages in the memory plane.
• Several bits that may be set and cleared through the EEFC interface, called general-purpose non-volatile
memory bits (GPNVM bits)
The embedded Flash size, the page size, the organization of lock regions and the definition of GPNVM bits are
specific to the device. The EEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’ command
has been issued by the application (see the “Get Flash Descriptor Command” section).
Figure 22-1. Flash Memory Areas
@FBA+0x000
User Signature Area
Unique Identifier Area
Unique Identifier
Code Area
@FBA+0x1FF
@FBA+0x000
@FBA+0x3FF
@FBA+0x000
Write “Start Unique Identifier”
(Flash Command STUI)
Write “Start User Signature”
(Flash Command STUS)
@FBA+0x010
@FBA+0x
010
Write “Stop Unique Identifier”
(Flash Command SPUI)
Write “Stop User signature”
(Flash Command SPUS)
FBA = Flash Base Address
SAM E70/S70/V70/V71 Family
Enhanced Embedded Flash Controller (EEFC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 128