Datasheet

46.7.24 USART Receiver Timeout Register
Name: US_RTOR
Offset: 0x0024
Reset: 0x0
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the USAR
T Write Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
TO[16]
Access
R/W
Reset 0
Bit 15 14 13 12 11 10 9 8
TO[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TO[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 16:0 – TO[16:0] T
imeout Value
Value Description
0
The receiver timeout is disabled.
1–65535
The receiver timeout is enabled and TO is Timeout Delay / Bit Period.
1–131071
The receiver timeout is enabled and TO is Timeout Delay / Bit Period.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1275