Datasheet

22. Enhanced Embedded Flash Controller (EEFC)
22.1 Description
The Enhanced Embedded Flash Controller (EEFC) provides the interface of the Flash block with the 32-bit internal
bus.
Its 128-bit wide memory interface increases performance. It also manages the programming, erasing, locking and
unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash
descriptor definition that informs the system about the Flash organization, thus making the software generic.
22.2 Embedded Characteristics
Increases Performance in Thumb-2 Mode with 128-bit-wide Memory Interface up to 150 MHz
Code Loop Optimization
128 Lock Bits, Each Protecting a Lock Region
9 General-purpose GPNVM Bits
One-by-one Lock Bit Programming
Commands Protected by a Keyword
Erase the Entire Flash
Erase by Sector
Erase by Page
Provides Unique Identifier
Provides 512-byte User Signature Area
Supports Erasing before Programming
Locking and Unlocking Operations
ECC Single and Multiple Error Flags Report
Supports Read of the Calibration Bits
Register Write Protection
22.3 Product Dependencies
22.3.1 Power Management
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has
no ef
fect on its behavior.
22.3.2 Interrupt Sources
The EEFC interrupt line is connected to the interrupt controller. Using the EEFC interrupt requires the interrupt
controller to be programmed first. The EEFC interrupt is generated only if the value of EEFC_FMR.FRDY is ‘1’.
22.4 Functional Description
22.4.1 Embedded Flash Organization
The embedded Flash interfaces directly with the internal bus. The embedded Flash is composed of:
One memory plane organized in several pages of the same size for the code
A separate 2 x 512-byte memory area which includes the unique chip identifier
A separate 512-byte memory area for the user signature
SAM E70/S70/V70/V71 Family
Enhanced Embedded Flash Controller (EEFC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 127