Datasheet

Value Description
1
The USART is configured as a slave node and a LIN Inconsistent synch field error has been detected
since the last RSTST
A.
Bit 25 – LINBE LIN Bit Error (cleared by writing a one to bit US_CR.RSTST
A)
Value Description
0
No bit error has been detected since the last RSTSTA.
1
A bit error has been detected since the last RSTSTA.
Bit 23 – LINBLS LIN Bus Line Status
Value Description
0
LIN bus line is set to 0.
1
LIN bus line is set to 1.
Bit 15 – LINTC LIN T
ransfer Completed (cleared by writing a one to bit US_CR.RSTSTA)
Value Description
0
The USART is idle or a LIN transfer is ongoing.
1
A LIN transfer has been completed since the last RSTSTA.
Bit 14 – LINID LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTST
A)
If USART operates in LIN Master mode (USART_MODE = 0xA):
If USART operates in LIN Slave mode (USART_MODE = 0xB):
Value Description
0
No LIN identifier has been sent since the last RSTSTA.
1
At least one LIN identifier has been sent since the last RSTSTA.
0
No LIN identifier has been received since the last RSTSTA.
1
At least one LIN identifier has been received since the last RSTSTA
Bit 13 – LINBK LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTST
A)
Applicable if USART operates in LIN master mode (USART_MODE = 0xA):
If USART operates in LIN Slave mode (USART_MODE = 0xB):
Value Description
0
No LIN break has been sent since the last RSTSTA.
1
At least one LIN break has been sent since the last RSTSTA
0
No LIN break has received sent since the last RSTSTA.
1
At least one LIN break has been received since the last RSTSTA.
Bit 9 – TXEMPTY T
ransmitter Empty (cleared by writing US_THR)
Value Description
0
There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1
There are no characters in US_THR, nor in the Transmit Shift Register.
Bit 8 – TIMEOUT Receiver T
imeout (cleared by writing a one to bit US_CR.RSTSTA)
Value Description
0
There has not been a timeout since the last start timeout command (STTTO in US_CR) or the Timeout
Register is 0.
1
There has been a timeout since the last start timeout command (STTTO in US_CR).
Bit 7 – PARE Parity Error (cleared by writing a one to bit US_CR.RSTST
A)
Value Description
0
No parity error has been detected since the last RSTSTA.
1
At least one parity error has been detected since the last RSTSTA.
Bit 6 – FRAME Framing Error (cleared by writing a one to bit US_CR.RSTST
A)
Value Description
0
No stop bit has been detected low since the last RSTSTA.
1
At least one stop bit has been detected low since the last RSTSTA.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1268