Datasheet

46.7.17 USART Channel Status Register
Name: US_CSR
Offset: 0x0014
Reset: 0x0
Property: Read-only
For SPI specific configuration, see “USAR
T Channel Status Register (SPI_MODE)”.
For LIN specific configuration, see “USART Channel Status Register (LIN_MODE)”.
For LON specific configuration, see “USART Channel Status Register (LON_MODE)”.
Bit 31 30 29 28 27 26 25 24
MANERR
Access
Reset 0
Bit 23 22 21 20 19 18 17 16
CTS DCD DSR RI CTSIC DCDIC DSRIC RIIC
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
NACK ITER TXEMPTY TIMEOUT
Access
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PARE FRAME OVRE RXBRK TXRDY RXRDY
Access
Reset 0 0 0 0 0 0
Bit 24 – MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTST
A)
Value Description
0
No Manchester error has been detected since the last RSTSTA.
1
At least one Manchester error has been detected since the last RSTSTA.
Bit 23 – CTS Image of CTS Input
Value Description
0
CTS input is driven low.
1
CTS input is driven high.
Bit 22 – DCD Image of DCD Input
Value Description
0
DCD input is driven low.
1
DCD input is driven high.
Bit 21 – DSR Image of DSR Input
Value Description
0
DSR input is driven low.
1
DSR input is driven high.
Bit 20 – RI Image of RI Input
Value Description
0
RI input is driven low.
1
RI input is driven high.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1262