Datasheet

46.7.15 USART Interrupt Mask Register (LIN_MODE)
Name: US_IMR (LIN_MODE)
Offset: 0x0010
Reset: 0x0
Property: Read-only
This configuration is relevant only if USART_MODE = 0xA or 0xB in the USAR
T Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Interrupt Mask
Bit 31 30 29 28 27 26 25 24
LINHTE LINSTE LINSNRE LINCE LINIPE LINISFE LINBE
Access
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
LINTC LINID LINBK TXEMPTY TIMEOUT
Access
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PARE FRAME OVRE TXRDY RXRDY
Access
Reset 0 0 0 0 0
Bit 31 – LINHTE LIN Header T
imeout Error Interrupt Mask
Bit 30 – LINSTE LIN Synch Tolerance Error Interrupt Mask
Bit 29 – LINSNRE LIN Slave Not Responding Error Interrupt Mask
Bit 28 – LINCE LIN Checksum Error Interrupt Mask
Bit 27 – LINIPE LIN Identifier Parity Interrupt Mask
Bit 26 – LINISFE LIN Inconsistent Synch Field Error Interrupt Mask
Bit 25 – LINBE LIN Bus Error Interrupt Mask
Bit 15 – LINTC LIN Transfer Completed Interrupt Mask
Bit 14 – LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask
Bit 13 – LINBK LIN Break Sent or LIN Break Received
Bit 9 – TXEMPTY TXEMPTY Interrupt Mask
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1259