Datasheet

46.7.13 USART Interrupt Mask Register
Name: US_IMR
Offset: 0x0010
Reset: 0x0
Property: Read-only
For SPI specific configuration, see “USAR
T Interrupt Mask Register (SPI_MODE)”.
For LIN specific configuration, see “USART Interrupt Mask Register (LIN_MODE)”.
For LON specific configuration, see “USART Interrupt Mask Register (LON_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Bit 31 30 29 28 27 26 25 24
MANE
Access
Reset 0
Bit 23 22 21 20 19 18 17 16
CTSIC DCDIC DSRIC RIIC
Access
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
NACK ITER TXEMPTY TIMEOUT
Access
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PARE FRAME OVRE RXBRK TXRDY RXRDY
Access
Reset 0 0 0 0 0 0
Bit 24 – MANE Manchester Error Interrupt Mask
Bit 19 – CTSIC Clear to Send Input Change Interrupt Mask
Bit 18 – DCDIC Data Carrier Detect Input Change Interrupt Mask
Bit 17 – DSRIC Data Set Ready Input Change Mask
Bit 16 – RIIC Ring Indicator Input Change Mask
Bit 13 – NACK
Non Acknowledge Interrupt Mask
Bit 10 – ITER Max Number of Repetitions Reached Interrupt Mask
Bit 9 – TXEMPTY TXEMPTY Interrupt Mask
Bit 8 – TIMEOUT Timeout Interrupt Mask
Bit 7 – PARE Parity Error Interrupt Mask
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
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echnology Inc.
Datasheet
DS60001527D-page 1256