Datasheet

46.7.9 USART Interrupt Disable Register
Name: US_IDR
Offset: 0x000C
Property: Write-only
For SPI specific configuration, see “USAR
T Interrupt Disable Register (SPI_MODE)”.
For LIN specific configuration, see “USART Interrupt Disable Register (LIN_MODE)”.
For LON specific configuration, see “USART Interrupt Disable Register (LON_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
MANE
Access
Reset
Bit 23 22 21 20 19 18 17 16
CTSIC DCDIC DSRIC RIIC
Access
Reset
Bit 15 14 13 12 11 10 9 8
NACK ITER TXEMPTY TIMEOUT
Access
Reset
Bit 7 6 5 4 3 2 1 0
PARE FRAME OVRE RXBRK TXRDY RXRDY
Access
Reset
Bit 24 – MANE Manchester Error Interrupt Disable
Bit 19 – CTSIC Clear to Send Input Change Interrupt Disable
Bit 18 – DCDIC Data Carrier Detect Input Change Interrupt Disable
Bit 17 – DSRIC Data Set Ready Input Change Disable
Bit 16 – RIIC Ring Indicator Input Change Disable
Bit 13 – NACK
Non Acknowledge Interrupt Disable
Bit 10 – ITER Max Number of Repetitions Reached Interrupt Disable
Bit 9 – TXEMPTY TXEMPTY Interrupt Disable
Bit 8 – TIMEOUT Timeout Interrupt Disable
Bit 7 – PARE Parity Error Interrupt Disable
Bit 6 – FRAME Framing Error Interrupt Disable
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
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echnology Inc.
Datasheet
DS60001527D-page 1250