Datasheet

46.7.6 USART Interrupt Enable Register (SPI_MODE)
Name: US_IER (SPI_MODE)
Offset: 0x0008
Property: Write-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USAR
T Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
NSSE
Access
Reset
Bit 15 14 13 12 11 10 9 8
UNRE TXEMPTY
Access
Reset
Bit 7 6 5 4 3 2 1 0
OVRE TXRDY RXRDY
Access
Reset
Bit 19 – NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable
Bit 10 – UNRE SPI Underrun Error Interrupt Enable
Bit 9 – TXEMPTY
TXEMPTY Interrupt Enable
Bit 5 – OVRE Overrun Error Interrupt Enable
Bit 1 – TXRDY TXRDY Interrupt Enable
Bit 0 – RXRDY RXRDY Interrupt Enable
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
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echnology Inc.
Datasheet
DS60001527D-page 1246