Datasheet

46.7.5 USART Interrupt Enable Register
Name: US_IER
Offset: 0x0008
Property: Write-only
For SPI specific configuration, see “USAR
T Interrupt Enable Register (SPI_MODE)”.
For LIN specific configuration, see “USART Interrupt Enable Register (LIN_MODE)”.
For LON specific configuration, see “USART Interrupt Enable Register (LON_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
MANE CTSIC DCDIC DSRIC RIIC
Access
Reset
Bit 15 14 13 12 11 10 9 8
NACK ITER TXEMPTY TIMEOUT
Access
Reset
Bit 7 6 5 4 3 2 1 0
PARE FRAME OVRE RXBRK TXRDY RXRDY
Access
Reset
Bit 20 – MANE Manchester Error Interrupt Enable
Bit 19 – CTSIC Clear to Send Input Change Interrupt Enable
Bit 18 – DCDIC Data Carrier Detect Input Change Interrupt Enable
Bit 17 – DSRIC Data Set Ready Input Change Enable
Bit 16 – RIIC Ring Indicator Input Change Enable
Bit 13 – NACK
Non Acknowledge Interrupt Enable
Bit 10 – ITER Max number of Repetitions Reached Interrupt Enable
Bit 9 – TXEMPTY TXEMPTY Interrupt Enable
Bit 8 – TIMEOUT Timeout Interrupt Enable
Bit 7 – PARE Parity Error Interrupt Enable
Bit 6 – FRAME Framing Error Interrupt Enable
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
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echnology Inc.
Datasheet
DS60001527D-page 1244