Datasheet

46.7.4 USART Mode Register (SPI_MODE)
Name: US_MR (SPI_MODE)
Offset: 0x0004
Reset: 0x0
Property: Read/Write
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USAR
T Mode Register.
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
– Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF):
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
WRDBT CLKO CPOL
Access
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
CPHA
Access
Reset 0
Bit 7 6 5 4 3 2 1 0
CHRL[1:0] USCLKS[1:0] USART_MODE[3:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 20 – WRDBT W
ait Read Data Before Transfer
Value Description
0
The character transmission starts as soon as a character is written into US_THR (assuming TXRDY
was set).
1
The character transmission starts when a character is written and only if RXRDY flag is cleared
(Receive Holding Register has been read).
Bit 18 – CLKO Clock Output Select
Value Description
0
The USART does not drive the SCK pin.
1
The USART drives the SCK pin if USCLKS does not select the external clock SCK.
Bit 16 – CPOL SPI Clock Polarity
Applicable if USAR
T operates in SPI mode (Slave or Master, USART_MODE = 0xE or 0xF):
CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to produce the
required clock/data relationship between master and slave devices.
Value Description
0
The inactive state value of SPCK is logic level zero.
1
The inactive state value of SPCK is logic level one.
Bit 8 – CPHA SPI Clock Phase
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
Value Description
0
Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1242