Datasheet

46.7.2 USART Control Register (SPI_MODE)
Name: US_CR (SPI_MODE)
Offset: 0x0000
Property: Write-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USAR
T Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RCS FCS
Access
Reset
Bit 15 14 13 12 11 10 9 8
RSTSTA
Access
Reset
Bit 7 6 5 4 3 2 1 0
TXDIS TXEN RXDIS RXEN RSTTX RSTRX
Access
Reset
Bit 19 – RCS Release SPI Chip Select
Applicable if USAR
T operates in SPI Master mode (USART_MODE = 0xE):
Value Description
0
No effect.
1
Releases the Slave Select Line NSS (RTS pin).
Bit 18 – FCS Force SPI Chip Select
Applicable if USAR
T operates in SPI Master mode (USART_MODE = 0xE):
Value Description
0
No effect.
1
Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to
address SPI slave devices supporting the CSAA
T mode (Chip Select Active After Transfer).
Bit 8 – RSTSTA Reset Status Bits
Value Description
0
No effect.
1
Resets the status bits OVRE, UNRE in US_CSR.
Bit 7 – TXDIS T
ransmitter Disable
Value Description
0
No effect.
1
Disables the transmitter.
Bit 6 – TXEN T
ransmitter Enable
Value Description
0
No effect.
1
Enables the transmitter if TXDIS is 0.
Bit 5 – RXDIS Receiver Disable
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1237