Datasheet

Value Description
0
No effect.
1
Drives the pin DTR to 0.
Bit 15 – RETTO Start T
imeout Immediately
Value Description
0
No effect
1
Immediately restarts timeout period.
Bit 14 – RSTNACK Reset Non Acknowledge
Value Description
0
No effect
1
Resets NACK in US_CSR.
Bit 13 – RSTIT Reset Iterations
Value Description
0
No effect.
1
Resets ITER in US_CSR. No effect if the ISO7816 is not enabled.
Bit 12 – SENDA Send Address
Value Description
0
No effect.
1
In Multidrop mode only, the next character written to the US_THR is sent with the address bit set.
Bit 11 – STTTO Clear TIMEOUT Flag and Start T
imeout After Next Character Received
Value Description
0
No effect.
1
Starts waiting for a character before enabling the timeout counter. Immediately disables a timeout
period in progress. Resets the status bit TIMEOUT in US_CSR.
Bit 10 – STPBRK Stop Break
Value Description
0
No effect.
1
Stops transmission of the break after a minimum of one character length and transmits a high level
during 12-bit periods. No ef
fect if no break is being transmitted.
Bit 9 – STTBRK Start Break
Value Description
0
No effect.
1
Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register
have been transmitted. No ef
fect if a break is already being transmitted.
Bit 8 – RSTSTA Reset Status Bits
Value Description
0
No effect.
1
Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINISFE, LINIPE, LINCE, LINSNRE,
LINSTE, LINHTE, LINID, LINTC, LINBK
and RXBRK in US_CSR.
Bit 7 – TXDIS T
ransmitter Disable
Value Description
0
No effect.
1
Disables the transmitter.
Bit 6 – TXEN T
ransmitter Enable
Value Description
0
No effect.
1
Enables the transmitter if TXDIS is 0.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1235