Datasheet

...........continued
Offset Name Bit Pos.
0x10
US_IMR
(LIN_MODE)
7:0 PARE FRAME OVRE TXRDY RXRDY
15:8 LINTC LINID LINBK TXEMPTY TIMEOUT
23:16
31:24 LINHTE LINSTE LINSNRE LINCE LINIPE LINISFE LINBE
0x10
US_IMR
(LON_MODE)
7:0 LCRCE LSFE OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16
31:24 LBLOVFE LRXD LFET LCOL LTXD
0x14 US_CSR
7:0 PARE FRAME OVRE RXBRK TXRDY RXRDY
15:8 NACK ITER TXEMPTY TIMEOUT
23:16 CTS DCD DSR RI CTSIC DCDIC DSRIC RIIC
31:24 MANERR
0x14
US_CSR
(SPI_MODE)
7:0 OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16 NSS NSSE
31:24
0x14
US_CSR
(LIN_MODE)
7:0 PARE FRAME OVRE TXRDY RXRDY
15:8 LINTC LINID LINBK TXEMPTY TIMEOUT
23:16 LINBLS
31:24 LINHTE LINSTE LINSNRE LINCE LINIPE LINISFE LINBE
0x14
US_CSR
(LON_MODE)
7:0 LCRCE LSFE OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16
31:24 LBLOVFE LRXD LFET LCOL LTXD
0x18 US_RHR
7:0 RXCHR[7:0]
15:8 RXSYNH RXCHR[8]
23:16
31:24
0x1C US_THR
7:0 TXCHR[7:0]
15:8 TXSYNH TXCHR[8]
23:16
31:24
0x20 US_BRGR
7:0 CD[7:0]
15:8 CD[15:8]
23:16 FP[2:0]
31:24
0x24 US_RTOR
7:0 TO[7:0]
15:8 TO[15:8]
23:16 TO[16]
31:24
0x28 US_TTGR
7:0 TG[7:0]
15:8
23:16
31:24
0x28
US_TTGR
(LON_MODE)
7:0 PCYCLE[7:0]
15:8 PCYCLE[15:8]
23:16 PCYCLE[23:16]
31:24
0x2C
...
0x3F
Reserved
0x40 US_FIDI
7:0 FI_DI_RATIO[7:0]
15:8 FI_DI_RATIO[15:8]
23:16
31:24
0x40
US_FIDI
(LON_MODE)
7:0 BETA2[7:0]
15:8 BETA2[15:8]
23:16 BETA2[23:16]
31:24
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1231