Datasheet

46.7 Register Summary
Offset Name Bit Pos.
0x00 US_CR
7:0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX
15:8 RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA
23:16 LINWKUP LINABT RTSDIS RTSEN DTRDIS DTREN
31:24
0x00
US_CR
(SPI_MODE)
7:0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX
15:8 RSTSTA
23:16 RCS FCS
31:24
0x04 US_MR
7:0 CHRL[1:0] USCLKS[1:0] USART_MODE[3:0]
15:8 CHMODE[1:0] NBSTOP[1:0] PAR[2:0] SYNC
23:16 INVDATA VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF
31:24 ONEBIT MODSYNC MAN FILTER MAX_ITERATION[2:0]
0x04
US_MR
(SPI_MODE)
7:0 CHRL[1:0] USCLKS[1:0] USART_MODE[3:0]
15:8 CPHA
23:16 WRDBT CLKO CPOL
31:24
0x08 US_IER
7:0 PARE FRAME OVRE RXBRK TXRDY RXRDY
15:8 NACK ITER TXEMPTY TIMEOUT
23:16 MANE CTSIC DCDIC DSRIC RIIC
31:24
0x08
US_IER
(SPI_MODE)
7:0 OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16 NSSE
31:24
0x08
US_IER
(LIN_MODE)
7:0 PARE FRAME OVRE TXRDY RXRDY
15:8 LINTC LINID LINBK TXEMPTY TIMEOUT
23:16
31:24 LINHTE LINSTE LINSNRE LINCE LINIPE LINISFE LINBE
0x08
US_IER
(LON_MODE)
7:0 LCRCE LSFE OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16
31:24 LBLOVFE LRXD LFET LCOL LTXD
0x0C US_IDR
7:0 PARE FRAME OVRE RXBRK TXRDY RXRDY
15:8 NACK ITER TXEMPTY TIMEOUT
23:16 CTSIC DCDIC DSRIC RIIC
31:24 MANE
0x0C
US_IDR
(SPI_MODE)
7:0 OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16 NSSE
31:24
0x0C
US_IDR
(LIN_MODE)
7:0 PARE FRAME OVRE TXRDY RXRDY
15:8 LINTC LINID LINBK TXEMPTY TIMEOUT
23:16
31:24 LINHTE LINSTE LINSNRE LINCE LINIPE LINISFE LINBE
0x0C
US_IDR
(LON_MODE)
7:0 LCRCE LSFE OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16
31:24 LBLOVFE LRXD LFET LCOL LTXD
0x10 US_IMR
7:0 PARE FRAME OVRE RXBRK TXRDY RXRDY
15:8 NACK ITER TXEMPTY TIMEOUT
23:16 CTSIC DCDIC DSRIC RIIC
31:24 MANE
0x10
US_IMR
(SPI_MODE)
7:0 OVRE TXRDY RXRDY
15:8 UNRE TXEMPTY
23:16 NSSE
31:24
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1230