Datasheet

• LIN master node (USART_MODE = 0xA)
•
LIN slave node (USART_MODE = 0xB)
In order to avoid unpredictable behavior, any change of the LIN node configuration must be followed by a software
reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See
“Receiver and Transmitter Control”.)
46.6.9.2 Baud Rate Configuration
See “Baud Rate in Asynchronous Mode”
•
LIN master node: The baud rate is configured in US_BRGR.
• LIN slave node: The initial baud rate is configured in US_BRGR. This configuration is automatically copied in the
LIN Baud Rate register (US_LINBRR) when writing US_BRGR. After the synchronization procedure, the baud
rate is updated in US_LINBRR.
46.6.9.3 Receiver and Transmitter Control
See “Receiver and T
ransmitter Control”
46.6.9.4 Character Transmission
See “T
ransmitter Operations”.
46.6.9.5 Character Reception
See “Receiver Operations”.
46.6.9.6 Header Transmission (Master Node Configuration)
All the LIN frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch
Field and Identifier Field.
So in master node configuration, the frame handling starts with the sending of the header
.
The header is transmitted as soon as the identifier is written in the LIN Identifier register (US_LINIR). At this moment
the flag TXRDY falls.
The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other.
The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the
Identifier corresponds to the character written in the LIN Identifier register (US_LINIR). The Identifier parity bits can
be automatically computed and sent (see “Identifier Parity”).
The flag TXRDY rises when the identifier character is transferred into the Shift register of the transmitter.
As soon as the Synch Break Field is transmitted, US_CSR.LINBK is set to ‘1’. Likewise, as soon as the Identifier
Field is sent, US_CSR.LINID is set to ‘1’. These flags are reset by writing a ‘1’ to US_CR.RSTSTA.
Figure 46-39. Header Transmission
TXD
Baud Rate
Clock
Start
Bit
Write
US_LINIR
1 0 1 0 1 0 1 0
TXRDY
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55
US_LINIR
ID
US_CSR.LINID
US_CSR.LINBK
Write RSTSTA=1
in US_CR
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1208