Datasheet

The chip select line is deasserted for a period equivalent to three bits between the transmission of two data.
The transmitter reports two status bits in US_CSR: TXRDY (T
ransmitter Ready), which indicates that US_THR is
empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the
current character processing is completed, the last character written in US_THR is transferred into the Shift register
of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave mode and if a character must be sent while the US_THR is empty, the UNRE (Underrun
Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing
a 1 to the RSTSTA (Reset Status) bit in US_CR.
In SPI Master mode, the slave select line (NSS) is asserted at low level one t
bit
(t
bit
being the nominal time required to
transmit a bit) before the transmission of the MSB bit and released at high level one t
bit
after the transmission of the
LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum
delay of three t
bit
always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip
Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing a 1 to the RCS bit in the
US_CR. The slave select line (NSS) can be released at high level only by writing a ‘1’ to US_CR.FCS (for example,
when all data have been transferred to the slave device).
In SPI Slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character
transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least one
t
bit
before the first serial clock cycle corresponding to the MSB bit.
46.6.8.6 Character Reception
When a character reception is completed, it is transferred to US_RHR and US_CSR.RXRDY rises. If a character is
completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR
and overwrites the previous one. The OVRE bit is cleared by writing a ‘1’ to US_CR.RSTST
A.
To ensure correct behavior of the receiver in SPI Slave mode, the master device sending the frame must ensure a
minimum delay of one t
bit
between each character transmission. The receiver does not require a falling edge of the
slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present
on the slave select line (NSS) at least one t
bit
before the first serial clock cycle corresponding to the MSB bit.
46.6.8.7 Receiver Timeout
Because the receiver baud rate clock is active only during data transfers in SPI mode, a receiver timeout is
impossible in this mode, whatever the value is in US_R
TOR.TO.
46.6.9 LIN Mode
The LIN mode provides master node and slave node connectivity on a LIN bus.
The LIN (Local Interconnect Network) is a serial communication protocol which ef
ficiently supports the control of
mechatronic nodes in distributed automotive applications.
The main properties of the LIN bus are:
• Single master/multiple slaves concept
• Low-cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or
as a pure state machine.
• Self synchronization without quartz or ceramic resonator in the slave nodes
• Deterministic signal transmission
• Low cost single-wire implementation
• Speed up to 20 kbit/s
LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required.
The LIN mode enables processing LIN frames with a minimum of action from the microprocessor.
46.6.9.1 Modes of Operation
The USART can act either as a LIN master node or as a LIN slave node.
The node configuration is chosen by setting USAR
T_MR.USART_MODE:
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1207