Datasheet

...........continued
SPI Bus Protocol Mode CPOL CPHA
2 1 1
3 1 0
Figure 46-37. SPI Transfer Format (CPHA = 1, 8 bits per transfer)
6
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2 3 4 5 7 86
MISO
SPI Master -> RXD
SPI Slave -> TXD
Figure 46-38. SPI Transfer Format (CPHA = 0, 8 bits per transfer)
SCK
(CPOL = 0)
SCK
(CPOL = 1)
1 2 3 4 5 7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
2
2
6
46.6.8.4 Receiver and Transmitter Control
See “Receiver and T
ransmitter Control”.
46.6.8.5 Character Transmission
The characters are sent by writing in the US_THR. An additional condition for transmitting a character can be added
when the USAR
T is configured in SPI Master mode. In the USART_MR (SPI_MODE), the value of WRDBT can
prevent any character transmission (even if US_THR has been written) while the receiver side is not ready (character
not read). When WRDBT equals ‘0’, the character is transmitted whatever the receiver status. If WRDBT is set to ‘1’,
the transmitter waits for US_RHR to be read before transmitting the character (RXRDY flag cleared), thus preventing
any overflow (character loss) on the receiver side.
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1206