Datasheet

46.6.8.1 Modes of Operation
The USART can operate in SPI Master mode or in SPI Slave mode.
SPI Master mode is enabled by writing 0xE to US_MR.USAR
T_MODE. In this case, the SPI lines must be connected
as described below:
• The MOSI line is driven by the output pin TXD
• The MISO line drives the input pin RXD
• The SCK line is driven by the output pin SCK
• The NSS line is driven by the output pin RTS
SPI Slave mode is enabled by writing to 0xF US_MR.USART_MODE. In this case, the SPI lines must be connected
as described below:
• The MOSI line drives the input pin RXD
• The MISO line is driven by the output pin TXD
• The SCK line drives the input pin SCK
• The NSS line drives the input pin CTS
In order to avoid unpredictable behavior, any change of the SPI mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset). (See Receiver and Transmitter
Control).
46.6.8.2 Baud Rate
In SPI mode, the baud rate generator operates in the same way as in USART Synchronous mode. See “Baud Rate in
Synchronous Mode or SPI Mode”. However
, there are some restrictions:
In SPI Master mode:
• The external clock SCK must not be selected (USCLKS ≠ 0x3), and US_MR.CLKO must be written to ‘1’, in
order to generate correctly the serial clock on the SCK pin.
• To obtain correct behavior of the receiver and the transmitter, the value programmed in US_BRGR.CD must be
greater than or equal to 6.
• If the divided peripheral clock is selected, the value programmed in CD must be even to ensure a 50:50 mark/
space ratio on the SCK pin. This value can be odd if the peripheral clock is selected.
In SPI Slave mode:
• The external clock (SCK) selection is forced regardless of the value of the US_MR.USCLKS. Likewise, the value
written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART SCK pin.
• To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at
least 6 times lower than the system clock.
46.6.8.3 Data Transfer
Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending on CPOL
and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected using US_MR.CHRL and US_MR.MODE9. The nine bits are selected by setting
the MODE9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI mode (Master or Slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed using
US_MR.CPOL. The clock phase is programmed using US_MR.CPHA. These two parameters determine the edges of
the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states,
resulting in four possible combinations that are incompatible with one another
. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the
master must reconfigure itself each time it needs to communicate with a different slave.
Table 46-12. SPI Bus Protocol Mode
SPI Bus Protocol Mode CPOL CPHA
0 0 1
1 0 0
SAM E70/S70/V70/V71 Family
Universal Synchronous Asynchronous Receiver T
ransc...
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echnology Inc.
Datasheet
DS60001527D-page 1205